Rapid advances made in semiconductor fabrication processes enable the production of faster, more powerful, and less expensive semiconductor chips. Although the same principles for fabricating semiconductor chips are applied, there exist a wide array of different semiconductor fabrication processes. The particular fabrication process being utilized depends heavily on the type of chip being manufactured. For example, the semiconductor process for fabricating a memory chip is quite different than that of fabricating a microprocessor. Not only are there many different accepted processes for fabricating specific semiconductor chips, a particular process can be customized to meet the unique specifications and requirements of an end user. Furthermore, designers are continuously “tweaking” their processes in attempts to maximize a chip's performance. Even the slightest change to any one of many different variables in the semiconductor fabrication process can result in differing electrical characteristics of the final chip.
Consequently, every time a particular semiconductor fabrication process is modified, adapted, or otherwise altered, rigorous tests must be conducted to determine the electrical characteristics produced by that particular fabrication process. The most simplistic way to test a particular semiconductor fabrication process is to fabricate and measure the electrical characteristics of the fully functional chips made from that particular process. However, this is quite time consuming, labor intensive, and expensive.
Rather than laying out, fabricating, and testing an entire chip, designers have discovered that a chip's performance can be extrapolated by measuring certain electrical characteristics exhibited by the resultant wafer. One of the key indicators of performance relates to a wafer's exhibited polysilicon gate depletion. The polysilicon gate depletion can be characterized by fabricating a few, scattered “test” transistors. Based on these test transistors, Capacitance-Voltage (CV) measurements can be taken to determine the corresponding polysilicon gate depletion effect at those locations. And based in part from this observed polysilicon gate depletion effect, designers can accurately model the overall performance of chips, were they to be fabricated from this particular process. Thereby, designers can accurately predict the speed, power consumption, etc. of integrated circuits which are fabricated from a particular process by simply constructing a few test transistors and taking CV measurements instead of going through the full, rigorous manufacturing process.
FIG. 1 shows a MOSFET which is commonly used today to evaluate CV characteristics. This fully processed MOSFET structure includes a source and drain junction from which minority carriers can be supplied to form an inversion layer from which CV measurements can be taken. FIG. 2 shows a typical CV measurement for such a MOSFET. The Δ represents the polysilicon depletion effect.
Although fabricating a few test transistors is a more efficient way of evaluating the potentials of new fabrication processes, it can nonetheless be a complex, time-consuming, and expensive endeavor. A simple test MOSFET structure, such as the one shown in FIG. 1, can take upwards of forty or more process steps to implement.
Therefore, there exists a need in the semiconductor fabrication industry for an apparatus and method for more efficiently evaluating the electrical characteristics of wafers produced from a particular process. The present invention offers a unique, novel solution for evaluating semiconductor fabrication processes which is simpler, faster, and less expensive to implement than the currently practiced methodology.